About this course
Understand and build digital hardware: from Boolean logic gates through synchronous sequential circuits, finite state machines, and timing closure to a complete digital subsystem realized on a real FPGA using VHDL or Verilog. The course develops the hardware engineering mindset needed for defense, embedded, and signal-processing systems.
Course format. Thirteen weeks, four contact hours each: a two-hour lecture covering concepts and theory, and a two-hour practice session for hands-on HDL coding and FPGA lab work. The course is project-based; teams carry one digital design project end to end and present it three times, in weeks 5, 8, and 13.
What you will build
Designed and implemented a complete digital subsystem on FPGA: specified the system in VHDL or Verilog, synthesized and placed-and-routed it for a Xilinx or Intel target, verified functional correctness in simulation, closed timing with a static timing analysis report, and validated the design on hardware against a defined set of test vectors.
Expected outcomes
- Represent numbers in binary, hexadecimal, and two's complement and apply Boolean algebra to simplify logic expressions
- Design combinational circuits using truth tables, Karnaugh maps, and standard gate families
- Build sequential circuits from flip-flops and latches and analyze their timing behavior
- Model and implement finite state machines as Moore and Mealy machines in hardware description language
- Write synthesizable VHDL and Verilog for combinational, sequential, and hierarchical digital designs
- Explain FPGA architecture including LUTs, flip-flops, DSP blocks, block RAM, and routing fabric
- Synthesize and implement an HDL design on an FPGA target using vendor tools and interpret the results
- Perform static timing analysis, resolve setup and hold violations, and cross clock-domain signals safely
- Describe memory system types, bus protocols, and SoC integration strategies
- Design, simulate, and verify a digital subsystem using a structured HDL design and verification flow
Key topics
- Combinational and sequential logic
- Finite state machines
- VHDL and Verilog HDL
- FPGA implementation and timing
Theoretical foundations
The concepts and results this course rests on.
- Boolean algebra, De Morgan's laws, and two-level logic minimization with Quine-McCluskey and Karnaugh maps
- Shannon's switching circuit theory and the duality between combinational networks and Boolean functions
- The Mealy-Moore equivalence theorem and state minimization algorithms
- Synchronous sequential circuit timing: setup time, hold time, clock-to-Q delay, and the maximum clock frequency equation
- Metastability theory and synchronizer failure probability for cross-clock-domain signals
- FPGA lookup-table architecture and the mapping of logic to LUT-based cells
- Static timing analysis: arrival times, required times, slack, and the concept of critical paths
Prerequisites
This is a Year-3 course. It assumes the mandatory CS core: data structures and algorithms, operating systems, computer networks, databases, software engineering, and the core mathematics (linear algebra, probability and statistics, calculus, discrete mathematics). It additionally requires the specific prior courses listed below.
Course-specific prerequisites:
- Introduction to digital systems or computer organization
- Discrete mathematics and Boolean algebra
- Programming in any compiled language
Weekly schedule 13 weeks · lecture + practice
Foundations
Wk 1
Number systems and Boolean algebra
LectureBinary, octal, hexadecimal, and two's complement arithmetic; Boolean algebra postulates, theorems, and two-level logic representation with sum-of-products and product-of-sums forms.
PracticeConvert numbers between bases, simplify Boolean expressions algebraically, and verify equivalence with truth tables.
ProjectRepository established, target FPGA board configured, and initial design problem selected.
Wk 2
Combinational logic and minimization
LectureKarnaugh maps for 2-to-5 variables, Quine-McCluskey tabular minimization, hazards in combinational logic, and standard combinational building blocks: multiplexers, decoders, adders, comparators.
PracticeMinimize functions with K-maps, identify static and dynamic hazards, and build a ripple-carry adder from gates.
ProjectCombinational datapath component for the project specified and tested in simulation.
Wk 3
Sequential circuits and flip-flops
LectureSR, D, JK, and T flip-flops; latch versus flip-flop behavior; master-slave and edge-triggered designs; setup time, hold time, and propagation delay; registers, shift registers, and synchronous counters.
PracticeImplement and simulate a D flip-flop, a 4-bit shift register, and an up-down counter in VHDL or Verilog.
ProjectSequential control element for the project identified and initial HDL written.
Wk 4
Finite state machines
LectureMoore and Mealy FSM models, state diagrams, and state tables; state encoding strategies (binary, one-hot, Gray code); state minimization; Huffman-Mealy-Moore equivalence and the partition method for reducing states.
PracticeDesign a vending machine controller and a serial protocol detector as Moore and Mealy FSMs in HDL, simulate and verify state transitions.
ProjectControl FSM for the project designed as a state diagram and coded in HDL.
Milestone
Wk 5
Specification presentationPresentation
LectureScoping a digital design project: requirements, block diagram, FSM specification, datapath and control partitioning, resource estimates, and evaluation criteria.
PracticeSTUDENT PRESENTATION milestone, specification. Teams present their design problem, block diagram, FSM and datapath specification, HDL architecture plan, FPGA target, and evaluation criteria.
ProjectApproved design specification with block diagram, FSM, and HDL architecture plan.
HDL and FPGA
Wk 6
HDL design with VHDL and Verilog
LectureVHDL and Verilog language elements: entity and architecture, modules and ports, signal assignment, concurrent and sequential statements, processes, generate statements, and hierarchy with components and instantiation. Synthesizable versus simulation-only constructs.
PracticeWrite a parameterized ALU and a memory controller in both VHDL and Verilog; simulate with a self-checking testbench.
ProjectKey HDL modules written and functionally verified in simulation.
Wk 7
FPGA architecture and implementation flow
LectureFPGA internal architecture: LUT-based logic cells, flip-flops, carry chains, block RAM, DSP blocks, PLLs, and programmable routing; the implementation flow: synthesis, technology mapping, place-and-route, bitstream generation, and on-chip debugging with Integrated Logic Analyzer.
PracticeSynthesize an HDL design for a Basys 3 or DE10-Lite board, interpret the synthesis report and resource utilization, and generate and download a bitstream.
ProjectFirst working version of the project synthesized and downloaded to the FPGA target board.
Milestone
Wk 8
Interim demo presentationPresentation
LectureDemonstrating a digital design slice: showing a working HDL module on the FPGA board with a resource utilization and initial timing summary.
PracticeSTUDENT PRESENTATION milestone, interim demo. Teams demonstrate a working HDL module running on the FPGA, report resource utilization and initial timing slack, and describe remaining work.
ProjectCore HDL modules running on FPGA with a resource utilization and timing summary.
Timing and system design
Wk 9
Timing analysis and clock domains
LectureStatic timing analysis: data arrival time, required arrival time, and slack; setup and hold constraints; clock skew and jitter; clock domain crossing hazards; synchronizer design and metastability failure rate; asynchronous FIFO for safe CDC.
PracticeRun static timing analysis on the project design, identify and resolve a setup violation, and implement a two-stage synchronizer for a cross-domain signal.
ProjectAll inter-domain signals crossed safely; timing constraints applied and slack verified positive.
Wk 10
Memory systems
LectureSRAM and DRAM organization and timing; synchronous and asynchronous SRAM interfaces; FPGA block RAM instantiation and inference; FIFO design; DDR memory controllers and the DFI interface; cache hierarchy basics and the memory hierarchy trade-off.
PracticeInfer block RAM for a lookup table, design a synchronous FIFO with full and empty flags, and simulate correct read and write timing.
ProjectMemory subsystem integrated into the project design and verified with a read-write stress test.
Wk 11
Bus architectures and SoC integration
LectureOn-chip bus standards: AMBA AXI4, AXI4-Lite, and AHB; bus arbitration and interconnects; UART, SPI, and I2C peripheral interfaces; soft processor cores (MicroBlaze, NIOS II) and SoC integration using IP integrator; the role of the hardware abstraction layer.
PracticeCreate an AXI4-Lite slave peripheral, integrate it into a Vivado or Quartus block design with a soft processor, and communicate with it from embedded C firmware.
ProjectPeripheral interface added to the design; soft processor or UART control path validated end to end.
Integration
Wk 12
Design verification and testing
LectureVerification strategy: directed tests, constrained-random stimulus, and coverage-driven verification; SystemVerilog assertions for property checking; boundary scan and JTAG testing; Design-for-Test principles.
PracticeWrite a SystemVerilog assertion for a protocol property, build a constrained-random testbench for the project, and measure functional coverage.
ProjectComplete testbench with assertions and functional coverage report; design verified and ready for the final defense.
Milestone
Wk 13
Final demo and oral defensePresentation
LectureCourse synthesis: from Boolean algebra to a deployed FPGA digital system, and the design choices that shaped it.
PracticeSTUDENT PRESENTATION milestone, final demo with oral defense. Teams demonstrate the finished digital subsystem on FPGA, walk through their HDL architecture and verification strategy, present the timing closure report and resource utilization, and answer technical questions on design decisions.
ProjectFinal FPGA-implemented digital system with HDL source, testbench, timing report, and documentation.
AI tools in this course.
Students use AI assistants to accelerate HDL coding: generating boilerplate VHDL and Verilog module skeletons, writing self-checking testbenches, and refactoring FSM implementations between encoding styles. Assistants help interpret synthesis and timing reports by explaining critical path findings and suggesting constraint refinements. Students also use AI to generate initial AXI4 peripheral register maps and to explore trade-offs between resource-sharing and parallel datapath implementations. All AI-generated HDL must pass simulation and on-board validation; students verify each suggestion against the timing closure report and the functional coverage results before accepting it.
Student project
Each team designs and implements one digital subsystem across the term, progressing from an HDL specification to a verified, timing-closed FPGA implementation. The project grows weekly from combinational and sequential building blocks through a control FSM and datapath to a complete integrated system with memory and a peripheral interface. The same artifact is presented at the specification, interim, and final milestones.
Requirements
- Build a working FPGA implementation, not a simulation-only design.
- Be original: a real design problem, not a re-implementation of a lab tutorial or course demo.
- Show real depth: verified with a self-checking testbench, timing constraints applied, and on-board hardware validation.
- Carry one running project from specification to a deployed, defensible result across the whole term.
- Work in a team of three or four and defend the design at each of the three presentations (weeks 5, 8, and 13).
Example projects
Digital signal processor for audio filtering on FPGAAES encryption core with AXI4 interfaceUART communication controller with FIFO bufferingPWM motor controller with encoder feedbackVGA display controller with framebufferSPI flash controller with read-ahead cacheCustom RISC-V pipeline stage in HDL
Assessment & grading
Grading is project-based, with no written exam. Teams of three or four present one running project three times.
| Component | What it covers | Weight |
|---|---|---|
| Project · Specification | Presentation 1 (week 5): design problem, block diagram, FSM, and HDL plan | 20% |
| Project · Interim | Presentation 2 (week 8): working HDL modules on the FPGA with timing and resource reports | 30% |
| Project · Final | Presentation 3 (week 13): complete FPGA system with verification evidence and oral defense | 50% |
Tools & platforms
- Xilinx Vivado: synthesis, implementation, static timing analysis, and bitstream generation for Xilinx FPGAs
- Intel Quartus Prime: synthesis and implementation for Intel (Altera) FPGAs including DE10-Lite
- ModelSim / Questa: VHDL and Verilog simulation with waveform viewing
- Icarus Verilog and GTKWave: open-source Verilog simulation and waveform viewer
- VUnit: VHDL unit testing framework for automated regression testing
- cocotb: Python-based hardware verification framework for writing testbenches in Python
- Digilent Basys 3 and Intel DE10-Lite: FPGA development boards used for on-hardware validation
- SystemVerilog: for testbench assertions, constrained-random stimulus, and functional coverage
- Git: version control for HDL source, constraints, and testbenches
Free online courses
Existing free, video-based courses this course can build on, for self-study or as a teaching basis.
- MIT OCWComputation Structures (6.004)
- YouTubeDigital Electronics (Neso Academy)
- CourseraFPGA Design for Embedded Systems (University of Colorado)
In Hebrew · בעברית
- Campus ILמבוא למערכות ספרתיות
Primary literature
Seminal works for advanced study.
- PaperA Mathematical Theory of Communication
- PaperGedanken-Experiments on Sequential Machines
- PaperA Method for Synthesizing Sequential Circuits
References
Books and resources link to an online or publisher page.
- TextbookDigital Design, 6th Edition
- TextbookDigital Design and Computer Architecture, 2nd Edition
- TextbookVHDL for Programmable Logic
- DocumentationXilinx Vivado Design Methodology Guide
- DocumentationAMBA AXI and ACE Protocol Specification
Role in each concentration
| Concentration | Role |
|---|---|
| Intelligent Software Systems | Elective |
| Networking & Cyber Security | Elective |
| AI & Robotics | Elective |
| AI and Quantum Computing for Finance | Elective |
| Immersive Systems & Game Development | Elective |
| Defense Technologies & Autonomous Systems | Core · Semester 2 |