About this course
Examine security at the hardware and firmware level, where physical access, side channels, and constrained devices create distinct threats.
Course format. Thirteen weeks, four contact hours each: a two-hour lecture (concepts and theory) and a two-hour practice session. The course is project-based; teams carry one running project end to end and present it three times, in weeks 5, 8, and 13.
What you will build
Performed a full hardware security assessment of an embedded device, mapping UART and SPI interfaces, dumping and reverse-engineering firmware with binwalk and Ghidra, extracting an AES key by differential power analysis on ChipWhisperer, then adding masking, constant-time fixes, signed updates, and debug-port lockdown.
Expected outcomes
- Perform simple and differential power analysis against a cryptographic implementation and recover AES key bytes using the Hamming weight leakage model, trace alignment, and key-byte hypothesis testing with ChipWhisperer.
- Extract embedded firmware via JTAG, UART, and SPI flash dumping with flashrom and binwalk, then reverse-engineer control flow and authentication logic using Ghidra and angr.
- Probe and exploit hardware debug interfaces using OpenOCD and BusPirate, characterize JTAG and SWD access, and apply debug-port lockdown strategies.
- Analyze secure boot chain integrity, TrustZone TEE boundaries, TPM 2.0 PCR attestation, and HSM key protection against FIPS 140-3 criteria using Renode for emulation.
- Execute fault injection scenarios including voltage glitching and clock manipulation, and design countermeasures such as voltage monitors, redundancy, and anti-rollback mechanisms.
- Construct a hardware threat model using STRIDE-for-hardware and TARA risk analysis, enumerate the embedded attack surface, and propose a PUF-based or TPM-backed secure key generation and update-signing design.
Key topics
- Side-channel attacks
- Secure boot & TPM
- Firmware analysis
- Embedded threat models
Theoretical foundations
The concepts and results this course rests on.
- side-channel attacks: simple power analysis (SPA), differential power analysis (DPA), timing attacks, and EM emanation as the physical leakage model
- the Hamming weight leakage model, trace alignment, and key-byte hypothesis testing underlying correlation power analysis
- secure boot chain and hardware root of trust: BootROM immutability, TrustZone TEE, verified boot stages, and chain-of-trust
- TPM 2.0 architecture: PCR registers, key hierarchy, remote attestation protocol, and the TPM 2.0 command set
- firmware extraction pipeline: serial debug console access, flash memory dump techniques, file system carving, and Ghidra static control flow graph analysis
- hardware debug interfaces: boundary scan (IEEE 1149.1 JTAG), SWD protocol, on-chip debugger adapters, and debug port lockdown strategies
- physical unclonable functions: manufacturing variation entropy, challenge-response pairs, and PUF-based key generation
- fault injection attacks: voltage glitching, clock manipulation, laser injection, and countermeasures including voltage monitors and redundancy
- hardware security modules: FIPS 140-3 levels, tamper-evident response, key ceremony procedures, and HSM API design
- embedded threat modeling: attack surface enumeration, STRIDE for hardware, TARA risk analysis, and mitigation mapping
Prerequisites
This is a Year-3 course. It assumes the mandatory CS core: data structures and algorithms, operating systems, computer networks, databases, software engineering, and the core mathematics (linear algebra, probability and statistics, calculus, discrete mathematics). It additionally requires the specific prior courses listed below.
Course-specific prerequisites:
- Computer organization and architecture
- Operating systems
- C or embedded programming
Weekly schedule 13 weeks · lecture + practice
Foundations
Wk 1
Embedded threat modeling and attack surface
LectureIntroduce STRIDE-for-hardware, TARA risk analysis, attack surface enumeration, and the taxonomy of embedded system attacks (P10).
PracticeUse BusPirate to identify and probe exposed hardware interfaces on the target board; document the initial attack surface.
ProjectChoose the target device and produce its hardware threat model using TARA methodology.
Wk 2
Hardware debug interfaces
LectureCover JTAG IEEE 1149.1 boundary scan, SWD protocol, on-chip debugger adapters, and debug port lockdown strategies (P6).
PracticeConnect to the target via OpenOCD over JTAG and SWD; probe debug port protection state and read memory.
ProjectMap and characterize all hardware debug interfaces on the target device.
Firmware
Wk 3
Firmware extraction
LectureExplain serial debug console access, flash memory dump techniques, file system carving, and SPI bus analysis (P5).
PracticeDump SPI flash with flashrom; unpack and carve the firmware image with binwalk.
ProjectExtract the complete firmware image from the target device.
Wk 4
Firmware reverse engineering and vulnerability analysis
LectureExplain Ghidra static control flow graph analysis and decompilation for identifying authentication logic and hardcoded secrets; binary analysis with Radare2 (P5).
PracticeReverse-engineer the authentication mechanism in Ghidra; apply angr symbolic execution to identify logic flaws in critical code paths.
ProjectDocument the authentication mechanism, identified secrets, and firmware vulnerabilities.
Wk 5
Threat model and firmware analysis specificationPresentation
LectureReview how interface, firmware, and threat model findings combine into a structured attack plan; introduce side-channel concepts (P1).
PracticeTeam presentation: each team defends target selection, TARA threat model, and firmware analysis results.
ProjectFreeze the project specification and planned attack-chain document.
Side channels
Wk 6
Side-channel theory: SPA, timing, and EM attacks
LectureIntroduce simple power analysis (SPA), timing attacks, and EM emanation; the physical leakage model and how cryptographic operations create measurable side channels (P1).
PracticeSet up ChipWhisperer; capture power traces from an AES reference implementation and observe SPA leakage patterns.
ProjectBaseline power trace capture from the reference AES implementation on ChipWhisperer.
Wk 7
Differential power analysis and key recovery
LectureDerive the Hamming weight leakage model, trace alignment, and key-byte hypothesis testing underlying differential and correlation power analysis (P2).
PracticeRun a DPA attack on the ChipWhisperer reference platform to recover AES key bytes from power traces.
ProjectComplete a simulated DPA attack on the reference AES implementation with documented key recovery.
Wk 8
Fault injection attacksPresentation
LectureExplain voltage glitching, clock manipulation, laser injection, and hardware countermeasures including voltage monitors and redundancy (P8).
PracticeTeam presentation: interim demonstration of DPA attack results and firmware vulnerability findings from the target device.
ProjectPresent DPA results and firmware vulnerabilities; receive design feedback for the hardening phase.
Roots of trust
Wk 9
Secure boot and chain of trust
LectureCover BootROM immutability, TrustZone TEE, verified boot stages, and chain-of-trust for hardware root of trust design (P3).
PracticeUse Renode to emulate and analyze a secure boot implementation; attempt boot bypass via simulated fault injection on the signature verification step.
ProjectEvaluate the target boot integrity mechanism and design a secure boot hardening approach.
Wk 10
TPM and hardware key storage
LecturePresent TPM PCR registers, key hierarchy, remote attestation protocol, and the TPM 2.0 command set for sealed storage and attestation (P4).
PracticeExercise TPM 2.0 commands: key sealing to PCR values, PCR extension, and attestation verification using tpm2-tools.
ProjectDesign a TPM-backed key protection and attestation improvement for the target device.
Defenses
Wk 11
PUFs, HSMs, and key protection
LectureExplain PUF manufacturing variation entropy, challenge-response pairs, and PUF-based key generation (P7); and HSM FIPS 140-3 levels, tamper-evident response, key ceremony, and HSM API design (P9).
PracticeUse Frida for dynamic firmware instrumentation to analyze key storage and cryptographic routine behavior; assess HSM API integration patterns for the hardening design.
ProjectPrototype the secure key storage and cryptographic signing components of the hardening design.
Wk 12
Countermeasures, hardened firmware, and secure update pipeline
LectureDiscuss masking, constant-time coding, anti-fault redundancy, signed firmware update pipeline, anti-rollback, and debug-port lockdown (P8 countermeasures, P9).
PracticeApply constant-time fixes and binary patches with Radare2; verify the signed update pipeline with flashrom and lock down debug interfaces via OpenOCD configuration.
ProjectImplement countermeasures: constant-time crypto patch, signed update pipeline, and debug interface lockdown.
Capstone
Wk 13
Final assessment and defensePresentation
LectureSynthesize the full assessment lifecycle: from TARA threat model through firmware extraction and DPA key recovery to secure boot hardening and signed update pipeline.
PracticeTeam presentation: complete hardware security assessment with demonstrated attacks, implemented hardening, and oral defense of findings.
ProjectDeliver the complete hardware security assessment: firmware extraction, DPA attack on AES, secure boot design, and hardening report.
AI tools in this course.
Students use AI assistants to accelerate the slow parts of a hardware assessment: scripting ChipWhisperer capture and DPA analysis in Python, summarizing Ghidra decompilation of dumped firmware, and generating glue to parse SPI dumps and logic-analyzer traces. They prompt the assistant to identify candidate hardcoded keys and update-verification flaws in disassembled code, to write the statistical key-recovery analysis over power traces, and to draft masking and constant-time rewrites of a leaky routine. AI also drives tool automation (flashrom, OpenOCD, tpm2-tools) and helps interpret glitching results, but students confirm every claimed leak or recovered secret on the real bench, because power and fault behavior is physical and the assistant cannot see the oscilloscope.
Student project
Teams perform a complete hardware security assessment on a target embedded device: extract firmware via JTAG and UART access, reverse-engineer the firmware in Ghidra to identify the authentication mechanism, execute a simulated differential power analysis attack on a reference AES implementation with ChipWhisperer, and propose and prototype a secure boot hardening design with cryptographic signing and debug-port lockdown.
Requirements
- Build a working system, not a set of disconnected exercises.
- Be original: a new system that solves a real problem, not a re-implementation of a tutorial or course demo.
- Show real depth: real data, real users or realistic load, and engineering trade-offs that are measured rather than assumed.
- Carry one running project from specification to a deployed, defensible result across the whole term.
- Work in a team of three or four and defend the design at each of the three presentations (weeks 5, 8, and 13).
Example projects
Smart-lock teardown and attackIoT camera firmware auditAES key extraction by DPASecure-boot bypass studyRouter firmware vulnerability huntTPM-backed key-storage redesignGlitch-attack on a microcontrollerConstant-time hardening project
Assessment & grading
Grading is project-based, with no written exam. Teams of three or four present one running project three times.
| Component | What it covers | Weight |
|---|---|---|
| Project · Specification | Presentation 1 (week 5): problem, objectives, and architecture | 20% |
| Project · Interim | Presentation 2 (week 8): the working system demonstrated live | 30% |
| Project · Final | Presentation 3 (week 13): end-to-end demo with oral defense | 50% |
Tools & platforms
- ChipWhisperer: power-analysis and fault-injection platform
- Ghidra: firmware disassembly and reverse engineering
- binwalk: firmware extraction and analysis
- Saleae Logic: logic analyzer for bus sniffing
- flashrom: SPI flash dumping and writing
- OpenOCD: JTAG and SWD debugging
- QEMU: firmware emulation for dynamic analysis
- Bus Pirate: low-level bus interfacing
- tpm2-tools: TPM 2.0 experimentation and sealing
- radare2: binary analysis and patching
Free online courses
Existing free, video-based courses this course can build on, for self-study or as a teaching basis.
- CourseraHardware Security
In Hebrew · בעברית
- YouTube, ד"ר רועי יוזביץ' (אוניברסיטת אריאל)ARDUINO בעברית, ללמוד לתכנת בחינם (ד"ר רועי יוזביץ')
- YouTube, ד"ר רועי יוזביץ' (אוניברסיטת אריאל)קורס מיקרו-בקרים, אוניברסיטת אריאל (רועי יוזביץ')
Primary literature
Seminal works for advanced study.
References
Books and resources link to an online or publisher page.
- TextbookThe Hardware Hacking Handbook
- TextbookPower Analysis Attacks: Revealing the Secrets of Smart Cards
- TextbookPractical IoT Hacking
- DocumentationSP 800-147: BIOS Protection Guidelines
- DocumentationTPM 2.0 Library Specification
- DocumentationChipWhisperer Documentation
- PaperTiming Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems
Role in each concentration
| Concentration | Role |
|---|---|
| Intelligent Software Systems | Elective |
| Networking & Cyber Security | Core · Semester 2 |
| AI & Robotics | Elective |
| AI and Quantum Computing for Finance | Elective |
| Immersive Systems & Game Development | Elective |
| Defense Technologies & Autonomous Systems | Core · Semester 1 |